The present invention is related to semiconductor memory devices and methods of making the same and, more particularly, to nonvolatile memory devices and methods of making the same.
Nonvolatile memory devices are capable of retaining data that is stored therein even in the absence of a supply of power. Two types of nonvolatile memory devices are NAND and NOR types. A NAND flash memory device has a memory cell string that includes a string selection transistor, pluralities of memory cell transistors, and a ground selection transistor, which are connected with each other in a series circuit. The string selection transistor is connected to a bitline and the ground selection transistor is connected to a common source line.
In programming the NAND flash memory device, 0V is applied to a selected bitline while a power source voltage of 1.8˜3.3V is applied to the gate of the string selection transistor, causing a channel voltage of the selected bitline to be set to 0V. A high voltage Vpgm for programming is then applied to a selected wordline so as to carry out a programming operation by means of a Fowler-Nordheim (FN) tunneling effect. During the programming operation, erroneous programming may occur for another memory cell that shares the selected wordline with the selected memory cell but which is connected to the non-selected bitline. In an attempt to prevent such erroneous programming of the adjacent (non-selected) memory cell, an effective technique known as a self-boosting scheme may be used. One approach for inhibiting erroneous programming of a memory cell by use of a self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled “METHOD OF PROGRAMMING FLASH MEMORY EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN”.
A self-boosting scheme can include applying 0V to the gate of the ground selection transistor so as to interrupt a current path toward a ground voltage. The power source voltage Vcc is used as a program-inhibiting voltage which is applied to a deselected bitline and the gate of the string selection transistor. Thus, the source of the string selection transistor connected to the deselected bitline is charged up to the level of Vcc−Vth, where Vth denotes a threshold voltage of the string selection transistor. As a result, the string selection transistor is substantially biased in a shut-off state. Then, the selected wordline is supplied a high voltage Vpgm for programming while deselected wordlines are supplied a pass voltage Vpass, which causes a channel voltage of a cell transistor that is not selected for programming is boosted higher. Accordingly, it may be possible to prevent/inhibit programming of deselected memory cells. However, this process may also cause an unacceptable level of leakage current to be generated in a high-density NAND flash memory device.
For example, with reference to FIG. 1, when a voltage of 0V is applied to a source region 13 and to a gate electrode of the ground selection transistor connected to a deselected bitline, a voltage of a drain region 13′ is increased by a boosting action of a channel voltage. Thus, depletion regions 15 around the source and drain regions 13 and 13′ may connect with each other to cause a punch-through effect by which a channel current therethrough becomes uncontrollable. The boosted channel voltage may also cause a drain-induced barrier lowering (DIBL) effect. The punch-through and DIBL effects may readily generate leak currents therein, and may complicate the process to inhibit erroneous programming. Such “soft programming” problems can occur more often as length of the gate electrode becomes shorter (short-channel effects). The continuing trend toward higher integration density for memory devices can therefore lead to greater soft programming problems.